Surface and bulk micromachining technologies combined with the existing integrated circuit (IC) technologies have more and more potential to serve as a system-on-chip (SoC) design platform. New ideas can be rapidly implemented through the mature foundry service without worrying about the process complexity. High-aspect-rate CMOS-MEMS process was first reported by G. K. Fedder et al., Proc. MEMS '96, pp. 13-18, 1996. Top metal layer in this technology acts as a hard mask while performing post etching process. Up to now, it has been applied to make mechanical filter, accelerometers, gyroscopes, optical modulators, and radio frequency (RF) passive devices. However, there are many drawbacks in the previous COMS-MEMS process, for examples, input/output (I/O) pads including electrostatic discharge (ESD) circuits are destroyed by ion bombardment, CMOS transistors are damaged if there is no metal layer above them, a floating metal layer induces more parasitics and is not allowed especially in RF circuits, CMOS passivation layer is removed and thus moisture and dust can easily deteriorate circuit performance, and the top metal layer in CMOS process can not be used as interconnects or passive devices but serves as a hard mask for post dry etching process instead. Furthermore, there has not proposed evidence to show if thermal cycling effect existing in the post dry etching process does not influence the circuit performance.
Therefore, it is desired an improved process flow that can solve the above-mentioned problems and is fully CMOS compatible.